With the progress in silicon LSI technology in recent years, a linear image sensor, in which a one-dimensional array of photodetectors and a charge coupled device (hereinafter referred to as CCD) transferring signal charges generated in the photodetectors are combined on a semiconductor substrate, has been put to practical use. Photodiodes utilizing p-n junction or Schottky barrier diodes are used as the photodetectors. The linear image sensor is called a visible image sensor or an infrared image sensor, depending on a wavelength detected by the image sensor. Some of these image sensors are provided with an electron shutter mechanism for preventing saturation of signal charges in the photodetectors.
FIGS. 15(a) and 15(b) illustrate a prior art infrared linear image sensor with such an electron shutter mechanism, in which FIG. 15(a) is a plan view schematically showing a layout of elements constituting the sensor and FIG. 15(b) is a sectional view taken along a line XVb--XVb of FIG. 15(a).
In FIG. 15(a), an infrared linear image sensor 200 includes a p type silicon substrate 9, a one-dimensional array of infrared detectors 1, a CCD 12, and an overflow drain 13. The CCD 12 and the over-flow drain 13 are parallel to each other with the array of the infrared detectors 1 between. Each infrared detector 1 is connected to the CCD 12 through a transfer gate 4 which controls transfer of charges from the infrared detector 1 to the CCD 12. In addition, each infrared detector 1 is connected to the overflow drain 13 through a shutter gate 15 which controls transfer of charges from the infrared detector 1 to the overflow drain 13. Gates of transistors constituting the transfer gates 4 and the shutter gates 15 are connected to input terminals It and Is, respectively, and controlled by clock signals from the input terminals It and Is.
In this structure, the CCD 12 constitutes a charge transfer circuit which transfers signal charges generated in the infrared detectors 1 in a direction of the array of infrared detectors, and an output amplifier 8 is connected to an output end of the charge transfer circuit. The overflow drain 13 is biased with positive external voltage and signal charges generated in the detectors 1 are drawn into the overflow drain 13.
A description is given of a sectional structure of the linear image sensor 200 with reference to FIG. 15(b). In FIG. 15(b), reference numeral 10 designates a PtSi/Si Schottky barrier diode as the above-described infrared detector 1, which comprises a platinum silicide layer 1a selectively disposed on the p type silicon substrate 9 and a p type silicon region 9a contacting the platinum silicide layer 1a to produce a Schottky Junction. In addition, a guard ring 11 is disposed around the p type silicon region 9a, so that leakage current from the infrared detector 1 is reduced. The guard ring 11 and the platinum silicide layer 1a serve as a charge storage region of the infrared detector 1.
An n type impurity diffused region 12d as a CCD channel and an n type impurity diffused region as the overflow drain 13 are disposed at opposite sides of the p type silicon region 9a of the infrared detector 1 with prescribed intervals from the p type silicon region 9a. In addition, a CCD transfer gate 12a comprising polysilicon is disposed on the n type impurity region 12d through a gate insulating film 10a. The CCD transfer gate 12a is connected to an input terminal Ic through which a transfer clock signal is supplied to the CCD 12.
A p type impurity region 4b having a prescribed concentration is disposed between the guard ring 11 and the CCD channel 12d and a p type impurity region 15b having a prescribed concentration is disposed between the guard ring 11 and the n type impurity region of the overflow drain 13. Gate electrodes 4a and 15a comprising polysilicon are disposed on the p type impurity region 4b and the p type impurity region 15b, respectively, through gate insulating films 10a. Thus, transistors as the transfer gate 4 and the shutter gate 15 are constituted. Characteristics of the transistors, i.e., potential levels in their ON and OFF states, are varied by varying the concentrations of the n type impurity regions 4b and 15b. Therefore, the concentrations are set so that the potential levels of the transistors as the transfer gate and the shutter gate are equal to each other.
FIG. 16 is a schematic diagram for explaining operation of the transfer gate and the shutter gate in a charge read cycle Xr of the image sensor of FIGS. 15(a) and 15(b). FIGS. 17(a)-17(f) are schematic diagrams illustrating potential profiles during the charge read operation in a cross-section taken along a line XVb--XVb of FIG. 15(a). The charge read operation will be described using FIGS. 16 and 17(a)-17(f).
When a driving clock CLt of the transfer gate 4 rises at time Ta0, the transfer gate 4 opens, that is, the potential level of the transfer gate 4 falls to an ON level Et.sub.on from an OFF level Et.sub.off as shown in FIG. 17(f), and signal charges Cs.sub.2 stored in the photodetector 10 until then are transferred to the CCD channel 12d through the n type impurity region 4b. When the driving clock CLt falls at time Ta1, the potential level of the transfer gate 4 returns to the level Et.sub.off, and the transfer gate 4 closes. At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on (energy level .phi.t) of the transfer gate 4.
More specifically, when the transfer gate 4 opens, the platinum silicide layer 1a in its floating state is connected to the CCD channel 12d whose potential level is lower than the potential level of the platinum silicide layer 1a, whereby the signal charges Cs2 are transferred toward the CCD channel 12a through the platinum silicide layer la and the gate 4. When the transfer gate 4 is closed, the platinum silicide layer 1a is disconnected from the CCD channel 12d and returns to the floating state, so that the platinum silicide layer la is charged in accordance with the quantity of transferred charges. In addition, the transfer of signal charges is carried out until the potential level of the infrared detector 1 becomes equal to the lowered potential level Et.sub.on of the transfer gate 4.
Meanwhile, in the infrared detector 1, signal charges Cs1 are stored in accordance with the amount of incident infrared light during a period of Ta1&lt;t&lt;ta2, until the shutter gate 5 opens, as shown in FIG. 17(b). When the driving clock C1s of the shutter gate 5 rises at time Ta2, the shutter gate 5 opens, that is, potential level of the shutter gate 5 drops to an ON level Es.sub.on from an OFF level Es.sub.off as shown in FIG. 17(c), and the signal charges Cs1 stored in the photodetector 10 until then are drawn into the n type impurity region of the overflow drain 13 through the n type impurity region 15b. When the driving clock CLs falls time Ta3, the potential level of the shutter gate 5 returns to the level Es.sub.off and the shutter gate 5 closes as shown in FIG. 17(d). At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Es.sub.on of the shutter gate 5 (energy level .phi.s) like the above-described opening and closing operations of the transfer gate 4. This reset level .phi.s of the shutter gate 5 is equal to the reset level .phi.t of the transfer gate 4.
Thereafter, in the infrared detector 1, signal charges Cs2 are stored in accordance with the amount of incident infrared light as shown in FIG. 17(e) during a period of Ta3&lt;t&lt;ta4 until the transfer gate 5 opens, i.e., during a shutter period Xs. The signal charges Cs2 stored during the shutter period Xs are transferred to the CCD channel 12 within a pulse period of the driving clock Clt of the transfer gate 4, i.e., a period of Ta4.ltoreq.t&lt;Ta5 (FIG. 17(f)). Thereafter, the charge read operation from the infrared detector 1 to the CCD 12 is carried out in the charge read cycle Xr as described with respect to FIGS. 17(a) to 17(f).
In the charge read cycle Xr, the CCD 12 transfers signal charges from the infrared detector 1. Hereinafter, the charge transfer operation will be described with reference to FIGS. 18 to 20.
FIG. 18 is a plan view illustrating the structure of CCD transfer gates of the linear image sensor 200 and connections between the CCD transfer gates and driving clocks therefor. FIG. 19 is a schematic diagram illustrating waveforms of three phase driving clocks .phi.1 to .phi.3 for the CCD 12 in addition to the driving clocks CLt and CLs of FIG. 16. FIG. 20 is a schematic diagram for explaining transfer of signal charges in an infrared detector to a position corresponding to the next infrared detector in the CCD 12.
As shown in FIG. 18, the CCD 12 is a three-phase driving CCD which includes three transfer gates 12a to 12c for one infrared detector 1. In this structure, a transfer gate 4 is disposed between each infrared detector 1 and each transfer gate 12a, and signal charges generated in the infrared detector 1 are transferred to a region directly under the transfer gate 12a of the CCD channel 12d. In addition, a shutter gate 15 is disposed between each infrared detector 1 and the overflow drain 13.
As shown in FIG. 20, when a pulse of the driving clock CLt is applied to the transfer gate input I.sub.t in the period of Ta0.ltoreq.t&lt;Ta1 in which potential wells are formed directly under the transfer gates 12a, signal charges A to D are sent to the potential wells under the first transfer gates 12a from the respective infrared detectors 1. When the driving clock CLt falls at time Ta1, the charge transfer operation begins.
More specifically, phases of the CCD driving signals .phi.1 to .phi.3 are different by 120 degrees from each other. Therefore, the potential wells are formed beneath the first and second transfer gates 12a and 12b during the first transfer period of Ta1.ltoreq.t&lt;t1, directly beneath the second transfer gates 12b during the second transfer period of t1.ltoreq.t&lt;t2, and beneath the second and third transfer gates 12b and 12c during the third transfer period of t2.ltoreq.t&lt;t3. When the fourth transfer period of t3.ltoreq.t&lt;t4 and the fifth transfer period of t4.ltoreq.t&lt;t5 have passed, signal charges A to D are present in the potential wells beneath the next transfer gates 12a. That is, during the above-described period of Ta0.ltoreq.t&lt;t6, the signal charges A to D move a distance corresponding to one infrared detector. The CCD 12 repeats the transfer operation until the next rise of the driving clock CLt of the transfer gate 4 to finish the transfer operation.
In the linear image sensor 200 having the electron shutter mechanism, however, if the potential level .phi.t of the infrared detector 1 which is reset at the time of the opening and closing operations of the transfer gate 4 is different from the potential level .phi.s of the infrared detector 1 which is reset at the time of the opening and closing operations of the shutter gate 15 even to a small degree, an accurate amount of the infrared light cannot be detected. That is, the detector reset level .phi.t at the time of reading charges depends on characteristics of the transfer gate transistor and the detector reset level .phi.s at the time of sweeping charges depends on characteristics of the shutter gate transistor. Therefore, if there is a difference, even a slight difference, in characteristics between the transfer gate transistor and the shutter gate transistor due to variations in manufacturing, the reset level of the infrared detector at the time of transferring charges from the infrared detector to the CCD is unfavorably different from the reset level of the infrared detector at the time of sweeping charges into the overflow drain 13, whereby some signal charges remain in the infrared detector without being transferred to the CCD or excessive charge is transferred to the CCD.
This problem will be described in more detail. FIGS. 21(a)-21(f) and FIGS. 22(a)-22(f) illustrate potential profiles each corresponding to the potential profile of FIGS. 17(a)-17(f). FIGS. 21(a)-21(f) show a case where the potential level .phi.s of the infrared detector 1 which is reset at the time of sweeping charges is lower than the potential level .phi.t of the infrared detector 1 which is reset at the time of transferring charges. In this case, when the shutter gate 5 operates, charges CO are excessively drawn into the overflow drain in addition to the stored charges Cs1 as shown in FIG. 21(c). Thereafter, during the charge read operation, signal charges Cs3 at a storage level lower than the difference between the level Et.sub.on at the ON time of the transfer gate 4 and the level Es.sub.on at the ON time of the shutter gate 5, i.e., an energy difference of .phi.t-.phi.s, unfavorably remain in the infrared detector 1.
On the other hand, FIGS. 22(a)-22(f) show a case where the potential level .phi.s of the infrared detector 1 which is reset at the time of sweeping charges is higher than the potential level .phi.t of the infrared detector 1 which is reset at the time of transferring charges. In this case, when the shutter gate 5 operates, a part of the stored charges Cs1, i.e., charges Cs5, are only drawn into the overflow drain leaving charges Cs4 as shown in FIG. 22(c). Thereafter, during the charge read operation, charges Cs4 in a quantity equivalent to the difference between the level Et.sub.on at the ON time of the transfer gate 4 and the level Es.sub.on at the ON time of the shutter gate 5, i.e., an energy difference of .phi.t-.phi.s, are excessively sent to the CCD in addition to the signal charges Cs2. As the result, signal contrast is lowered.
In order to solve these problems, an improved linear image sensor has been developed by the inventor of the present invention.
FIGS. 23(a) and 23(b) are diagrams illustrating the improved linear image sensor, in which FIG. 23(a) is a plan view schematically showing a layout of elements constituting the sensor and FIG. 23(b) is a sectional view taken along a line XXIIIb--XXIIIb of FIG. 23(a). In these figures, reference numeral 300 designates the improved linear image sensor. In the sensor 300, an overflow drain 3 and a CCD 12 are disposed on one side of an array of infrared detectors 1 and the CCD 12 is disposed between the overflow drain 3 and the infrared detector array. Shutter gates 5 are disposed between the CCD 12 and the overflow drain 3, so that signal charges generated in the infrared detector array are drawn into the overflow drain 3 through the CCD 12. In addition, a p type impurity region 5b is disposed between a transfer channel 12b of the CCD 12 and an n type impurity region of the overflow drain 3, and a polysilicon gate 5a is disposed on the p type impurity region 5b through a gate insulating film 10a. The p type region 5b and the polysilicon gate 5a constitute a shutter gate transistor. Other structures are the same as those of the linear image sensor shown in FIG. 15.
FIG. 24 is a plan view illustrating a structure of CCD transfer gates of the linear image sensor 300 and connections between the CCD transfer gates and driving clocks therefor. FIGS. 25(a)-25(g) are schematic diagrams illustrating potential profiles during a charge read operation of the linear image sensor 300 in a cross-section taken along the line XXIIIb--XXIIIb of FIG. 23(a). FIG. 26 is a schematic diagram illustrating waveforms of signals applied to the respective gates of the linear image sensor 300. The charge read operation will be described using these figures.
First of all, when the driving clock CLt of the transfer gate 4 rises at time Ta0, the transfer gate 4 opens, that is, the potential level of the gate 4 falls to an ON level Et.sub.on from an OFF level Et.sub.off, and signal charges Cs stored in the infrared detector 1 until then are transferred to the CCD channel 12d through the n type impurity region 4b (FIG. 25(f)). When the driving clock CLt falls at time Ta1, the potential level of the gate 4 returns to the level Et.sub.off and the gate 4 closes. At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on of the transfer gate 4 (an energy level .phi.t) for the same reason as in the case of the sensor 200 shown in FIG. 15.
At the same time, charge transfer operation begins in the CCD 12. Thereafter, during the period of Ta1&lt;t&lt;Tb2 of FIG. 25(a), i.e., the transfer period Xt of FIG. 26, signal charges are successively stored in the infrared detector 1 as shown in FIG. 25(a) while the charge transfer operation is carried on in the CCD 12. Thereafter, during the period of Tb2.ltoreq.t&lt;Tb3, i.e., the period until the shutter gate 5 opens, signal charges Ce are stored in the infrared detector 1 in accordance with the amount of incident infrared light as shown in FIG. 25(b). When the driving clock CLs of the shutter gate 5 and the driving clock CLt of the transfer gate 4 rise at time Tb3, these gates 5 and 4 open, that is, the potential levels of the gates 5 and 4 fall to the ON levels Es.sub.on and Et.sub.on from the OFF levels Es.sub.off and Et.sub.off, respectively, whereby signal charges Ce stored in the infrared detector 1 are drawn into the n type impurity region of the overflow drain 3 through the channel 12b of the CCD 12.
When the driving clocks CLs and CLt rise at time Tb4, the potential levels of the gates 5 and 4 return to the levels of Es.sub.off and Et.sub.off, respectively, and the gates 5 and 4 close (FIG. 25(d)). At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on (.phi.t) of the transfer gate 4, regardless of the ON level Es.sub.on of the shutter gate 5, as in the case of the opening and closing operations of the transfer gate 4, so that the potential level of the infrared detector 1 in the charge read operation is not different from that in the charge drain operation.
Thereafter, in the infrared detector 1, signal charges Cs are stored in accordance with the amount of incident infrared light until the transfer gate 4 opens, during the shutter period Xs, i.e., the period of Tb4&lt;t&lt;Tb5 (FIG. 25(e)). Charges Cs stored during this period are transferred to the CCD channel 12 within the pulse period of the driving clock CLt of the transfer gate 4, i.e., the period of Tb5.ltoreq.t&lt;Tb6 (FIG. 25(f)). When the driving clock CLt rises at time Tb6, the CCD 12 begins the charge transfer operation. Thereafter, charges are successively transferred from the infrared detector 1 to the CCD 12 in the charge read cycle Xr as shown in FIGS. 25(a) to 25(g).
In order to achieve the above-described operation, it is necessary to set the potential levels to be increasingly deep in the order of the transfer gate (Et.sub.on), the CCD channel (E.sub.cc), the shutter gate (Es.sub.on) and the overflow drain (Eod). This is easily achieved by controlling impurity concentrations of the p type and n type impurity regions of the respective elements.
In the above-described linear image sensor 300, unnecessary charges generated in the infrared detector are drawn into the charge exhaust part like the overflow drain through the charge transfer part. This idea is also disclosed in Japanese Published Patent Applications 62-200761 and 60-120555. More specifically, Japanese Published Patent Application 62-200761 discloses a solid-state imaging element in which a charge transfer part is disposed between a one-dimensional array of infrared detectors and an overflow drain, and charges flowing into the charge transfer part due to excess light incident on the infrared detector are drawn into the overflow drain. However, this device has no electron shutter mechanism. In addition, Japanese Published Patent Application 60-120555 discloses a solid-state imaging device in which two CCD registers are disposed on opposite sides of a one-dimensional array of infrared detectors and two dummy shift registers are disposed on the outer sides of the CCD registers and charges remaining in the infrared detectors are drained into the dummy shift registers through the CCD shift registers.
In the above-described linear image sensor 300, since the signal charges Ce stored in the infrared detector 1 are drawn into the overflow drain 3 through the CCD 12, during charge drain operation 1 the charge transfer operation of the CCD 12, transferred signal charges are sometimes mixed with the drawn charges. In this case, the shutter gate 5 cannot be turned ON during the transfer operation of the CCD 12. In order to avoid this, the CCD transfer period and the charge drain period are set in different periods of time. However, the shutter period Xs is limited to a short period after the charge transfer period Xt in the charge read cycle Xr, so that signal charges are not sufficiently stored especially when the amount of incident infrared light is small.